In this paper, low power and high speed 8x8 Bit Vedic Multiplier is presented. A Novel technique for digit multiplication is produced that is quite different from the conventional method of multiplication like Add and Shift. This paper presents a systematic design methodology for fast and delay efficient Vedic Multiplier based on Vedic Mathematics. The multiplier architecture based on the Vertical and Crosswise algorithm of Ancient Indian Vedic Mathematics. In this paper, general technique for NxN multiplication is proposed and implemented; this gives less delay for calculating the multiplication results for 8x8 Bit Vedic Multiplier. In this paper, less delay and high speed 8x8 Bit Vedic Multiplier is presented. The multiplier cell of the adder is designed by using Pass Transistor (n-transistor), p-transistor used as cross coupled devices. The 8x8 Bit Vedic Multiplier circuit has been simulated using Microwind 3.1 VLSI Layout CAD tools. Simulated results for proposed 8x8 bit Vedic Multiplier circuit shows a great reduction in delay for 0.18 μm.